The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Jul. 24, 2009
Applicants:

Andrew G. Kegel, Redmond, WA (US);

Mark D. Hummel, Franklin, MA (US);

Stephen D. Glaser, San Francisco, CA (US);

Inventors:

Andrew G. Kegel, Redmond, WA (US);

Mark D. Hummel, Franklin, MA (US);

Stephen D. Glaser, San Francisco, CA (US);

Assignee:

ADVANCED MICRO DEVICES, INC., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/10 (2016.01); G06F 3/06 (2006.01); G06F 12/08 (2016.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1081 (2013.01); G06F 12/1009 (2013.01); G06F 3/0601 (2013.01); G06F 3/064 (2013.01); G06F 3/067 (2013.01); G06F 3/0631 (2013.01); G06F 3/0683 (2013.01); G06F 12/0292 (2013.01); G06F 12/063 (2013.01); G06F 12/0868 (2013.01); G06F 12/0882 (2013.01); G06F 12/0897 (2013.01);
Abstract

An IOMMU for controlling requests by an I/O device to a system memory of a computer system includes control logic and a cache memory. The control logic may translate an address received in a request from the I/O device. If the request includes a transaction layer protocol (TLP) packet with a process address space identifier (PASID) prefix, the control logic may perform a two-level guest translation. Accordingly, the control logic may access a set of guest page tables to translate the address received in the request. A pointer in a last guest page table points to a first table in a set of nested page tables. The control logic may use the pointer in a last guest page table to access the set of nested page tables to obtain a system physical address (SPA) that corresponds to a physical page in the system memory. The cache memory stores completed translations.


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