The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Jul. 28, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Stuart Z. Jacobs, Lakeville, MN (US);

David A. Larson, Rochester, MN (US);

Michael J. Vance, Rochester, MN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 9/455 (2006.01); G06F 12/0875 (2016.01); G06F 13/24 (2006.01); G06F 12/08 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0875 (2013.01); G06F 9/30054 (2013.01); G06F 9/45558 (2013.01); G06F 13/24 (2013.01); G06F 2009/45579 (2013.01); G06F 2212/452 (2013.01);
Abstract

Systems, methods, and computer program products to perform an operation, the operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a cache line address buffer location in a virtual processor, and responsive to the lightweight HDEC, writing, by the shared processor, a set of cache line addresses used by the first logical partition to the cache line address buffer location in the virtual processor.


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