The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Jan. 05, 2015
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventors:

Shuji Yamamura, Yokohama, JP;

Go Sugizaki, Machida, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0833 (2013.01); G06F 9/30047 (2013.01); G06F 9/30087 (2013.01); G06F 9/3834 (2013.01); G06F 9/3851 (2013.01); G06F 2212/621 (2013.01);
Abstract

An arithmetic processing device has a first arithmetic processing unit including a first instruction controller that controls a write instruction to a memory and a first cache unit, and a second arithmetic processing unit including a second instruction controller and a second cache unit. The first arithmetic processing unit transmits an invalidation request to the second arithmetic processing unit when a write request to the memory is issued within a first transaction, and in response to the invalidation request, the second cache unit determines whether a second transaction is to be aborted based on information in the invalidation request when the second transaction conflicts with the first transaction for a cache block corresponding to a destination of the write request, and sends a determination result to the first arithmetic processing unit.


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