The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Jun. 02, 2014
Applicant:

Nec Laboratories America, Inc., Princeton, NJ (US);

Inventors:

Nishkam Ravi, Mountain View, CA (US);

Yi Yang, Edison, NJ (US);

Srimat Chakradhar, Manalapan, NJ (US);

Bin Ren, Kennewick, WA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 13/30 (2006.01); G06F 9/45 (2006.01); G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0207 (2013.01); G06F 8/41 (2013.01); G06F 8/443 (2013.01); G06F 8/51 (2013.01); G06F 12/023 (2013.01); G06F 13/30 (2013.01); G06F 2212/1016 (2013.01);
Abstract

There are provided source-to-source transformation methods for a multi-dimensional array and/or a multi-level pointer for a computer program. A method includes minimizing a number of holes for variable length elements for a given dimension of the array and/or pointer using at least two stride values included in stride buckets. The minimizing step includes modifying memory allocation sites, for the array and/or pointer, to allocate memory based on the stride values. The minimizing step further includes modifying a multi-dimensional memory access, for accessing the array and/or pointer, into a single dimensional memory access using the stride values. The minimizing step also includes inserting offload pragma for a data transfer of the array and/or pointer prior as at least one of a single-dimensional array and a single-level pointer. The data transfer is from a central processing unit to a coprocessor over peripheral component interconnect express.


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Ravi, Nishkam. (2017). Automatic communication and optimization of multi-dimensional arrays for many-core coprocessor using static compiler analysis (U.S. Patent No. 9535826). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9535826

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