The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Feb. 09, 2015
Applicant:

Hgst Netherlands B.v., Amsterdam, NL;

Inventors:

Aniryudh Reddy Durgam, San Diego, CA (US);

Haritha Uppalapati, San Diego, CA (US);

Kiran Yalamanchi, San Diego, CA (US);

Assignee:

HGST Netherlands B.V., Amsterdam, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 11/56 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G11C 29/52 (2013.01); G11C 11/5628 (2013.01);
Abstract

A storage device may include a controller and a plurality of memory devices logically divided into a plurality of pages. Each page in the plurality of pages may include a plurality of bits. The controller may be configured to: apply a read level to a control gate of a transistor for each respective bit in the plurality of bits; determine, based on an amount of current that flows through the transistor, a respective value for each bit from the respective plurality of bits; determine, based on the respective values for the respective plurality of bits, an error ratio that indicates a number of bits from the plurality of bits that are written as a first bit value but are incorrectly read as a second bit value relative to a number of bits from the plurality of bits that are written as the second bit value but are incorrectly read as the first bit value; and adjust, based on the error ratio, the read level.


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