Efficient use of branch delay slots and branch prediction in pipelined computer architectures

Abstract

A pipelined processor selects an instruction fetch mode from a number of fetch modes including an executed branch fetch mode, a predicted fetch mode, and a sequential fetch mode. Each branch instruction is associated with branch delay slots, the size of which can be greater than or equal to zero, and can vary from one branch instance to another. Branch prediction is used to fetch instructions, with the source of information for predictions deriving from a last instruction in the branch delay slots. When a prediction error occurs, the executed branch fetch mode uses an address from branch instruction evaluation to fetch a next instruction.