The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Aug. 08, 2012
Applicants:

Bruce M. Fleischer, Bedford Hills, NY (US);

Thomas W. Fox, Hopewell Junction, NY (US);

Hans M. Jacobson, White Plains, NY (US);

Ravi Nair, Briarcliff Manor, NY (US);

Daniel A. Prener, Croton-on-Hudson, NY (US);

Inventors:

Bruce M. Fleischer, Bedford Hills, NY (US);

Thomas W. Fox, Hopewell Junction, NY (US);

Hans M. Jacobson, White Plains, NY (US);

Ravi Nair, Briarcliff Manor, NY (US);

Daniel A. Prener, Croton-on-Hudson, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 1/04 (2006.01); G06F 9/30 (2006.01); G06F 9/38 (2006.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30036 (2013.01); G06F 9/30065 (2013.01); G06F 9/3879 (2013.01); G06F 9/3887 (2013.01); G06F 15/8084 (2013.01);
Abstract

Embodiments relate to vector processing in an active memory device. An aspect includes a system for vector processing in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method including decoding an instruction with a plurality of sub-instructions to execute in parallel. An iteration count to repeat execution of the sub-instructions in parallel is determined. Execution of the sub-instructions is repeated in parallel for multiple iterations, by the processing element, based on the iteration count. Multiple locations in the memory are accessed in parallel based on the execution of the sub-instructions.


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