The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Nov. 25, 2010
Applicants:

Yeong Uk Seo, Seoul, KR;

Sung Woon Yoon, Seoul, KR;

Jin Su Kim, Seoul, KR;

Myoung Hwa Nam, Seoul, KR;

Sang Myung Lee, Seoul, KR;

Chi Hee Ahn, Seoul, KR;

Inventors:

Yeong Uk Seo, Seoul, KR;

Sung Woon Yoon, Seoul, KR;

Jin Su Kim, Seoul, KR;

Myoung Hwa Nam, Seoul, KR;

Sang Myung Lee, Seoul, KR;

Chi Hee Ahn, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/00 (2006.01); H05K 1/09 (2006.01); H05K 3/10 (2006.01); H05K 3/20 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 3/02 (2006.01);
U.S. Cl.
CPC ...
H05K 3/101 (2013.01); H05K 1/02 (2013.01); H05K 1/0353 (2013.01); H05K 1/092 (2013.01); H05K 3/20 (2013.01); H05K 3/02 (2013.01); H05K 3/108 (2013.01); H05K 2201/0376 (2013.01); H05K 2203/0278 (2013.01);
Abstract

The present invention provides a structure of a printed circuit board and a manufacturing method thereof. The method includes: (a) forming a circuit pattern on an insulating layer in which a seed layer is formed; (b) embedding the circuit pattern into the insulating layer by a press method; and (c) removing the seed layer. According to the present invention, a fine pattern may be formed without occurring alignment problem by forming a circuit pattern directly on an insulating layer and reliability of the formed fine pattern may be increased by performing a process of embedding protruded circuits into the insulating layer. In addition, possibility of inferior circuit occurring due to ion migration between adjacent circuits may be reduced by performing over-etching a circuit layer to be lower than a surface of the insulating layer during the etching process of removing a seed layer.


Find Patent Forward Citations

Loading…