The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Jan. 28, 2015
Applicant:

Ciena Corporation, Hanover, MD (US);

Inventors:

Corry Alexander Cordes, San Rafael, CA (US);

Harsha Vardhan Kovuru, Cotati, CA (US);

Balaji Subramaniam, Petaluma, CA (US);

Assignee:

Ciena Corporation, Hanover, MD (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/707 (2013.01); H04L 12/24 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
H04L 45/22 (2013.01); G06F 3/067 (2013.01); H04L 41/0654 (2013.01);
Abstract

A primary and secondary card are coupled to protect and working paths, respectively providing a redundant connection to a node. The primary and secondary cards implement an inter-card path that is a working path for the primary card and a protect path for the secondary card. Responsive to a fault in the working path, the secondary card generates a simulated error condition on the inter-card path, causing the primary card to make the protect path the active path. When the protect path is the active path and goes down, the primary card generates a simulated error condition on the inter-card path, causing the secondary card to make the working path the active path. Switching of packets to the active and protect paths on the primary and secondary cards and is performed by an FPGA that maintains its own state machine subject to instructions from software executed by the cards.


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