The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Mar. 17, 2015
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Tomohiro Oginoe, Yokkkaichi, JP;

Ryoichi Honma, Yokkaichi, JP;

Masanori Terahara, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/792 (2006.01); H01L 23/522 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 29/788 (2006.01); H01L 29/16 (2006.01); H01L 29/423 (2006.01); H01L 21/768 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/28273 (2013.01); H01L 21/28282 (2013.01); H01L 21/76897 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 29/16 (2013.01); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01); H01L 29/42376 (2013.01); H01L 29/4958 (2013.01); H01L 29/51 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7889 (2013.01); H01L 29/7926 (2013.01);
Abstract

A dielectric liner, a bottom conductive layer, and a stack of alternating layers including insulator layers and spacer material layers are sequentially formed over a substrate. A memory opening extending through the stack can be formed by an anisotropic etch process that employs the bottom conductive layer as an etch stop layer. The memory opening is extended downward by etching through the bottom conductive layer and the dielectric liner, while minimizing an overetch into the substrate. A memory stack structure can be formed in the memory opening. Subsequently, a backside contact trench can be formed through the stack employing the bottom conductive layer as an etch stop layer. The spacer material layers can be removed to form backside recesses, which are filled with a conductive material to form electrically conductive layers. The remaining portion of the bottom conductive layer can be employed as a source select gate electrode.


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