The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Nov. 14, 2014
Applicant:

Skyworks Solutions, Inc., Woburn, MA (US);

Inventors:

Ambarish Roy, Waltham, MA (US);

Eric Marsan, Lowell, MA (US);

Stephen Richard Moreschi, Peabody, MA (US);

Assignee:

Skyworks Solution, Inc., Woburn, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 3/04 (2006.01); H01L 27/06 (2006.01); H01L 21/8252 (2006.01); H03F 1/22 (2006.01); H03F 1/56 (2006.01); H03F 3/195 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 21/8252 (2013.01); H01L 27/0605 (2013.01); H03F 1/223 (2013.01); H03F 1/56 (2013.01); H03F 3/195 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15313 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19105 (2013.01); H03F 2200/135 (2013.01); H03F 2200/222 (2013.01); H03F 2200/294 (2013.01); H03F 2200/387 (2013.01); H03F 2200/451 (2013.01);
Abstract

Feedback and impedance circuits, devices and methods for broadband radio-frequency (RF) amplifiers. An RF amplifier architecture can include an amplifier having a first field-effect transistor (FET) and a second FET arranged in a cascode configuration. The gate of the first FET can be configured to receive an RF signal, the drain of the first FET can be coupled to the source of the second FET, and the drain of the second FET can be configured to output an amplified RF signal. The RF amplifier architecture can further include a first feedback circuit implemented between the drain of the second FET and the gate of the second FET to provide gain control, and a second feedback circuit implemented between the drain of the second FET and the gate of the first FET to provide an increase in a frequency range having a desirable range of gain.


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