The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Jan. 30, 2013
Applicant:

Infineon Technologies Dresden Gmbh, Dresden, DE;

Inventors:

Rolf Weis, Dresden, DE;

Michael Treu, Villach, AT;

Gerald Deboy, Klagenfurt, AT;

Armin Willmeroth, Augsburg, DE;

Hans Weber, Bayerisch Gmain, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/02 (2006.01); H01L 21/84 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 27/12 (2006.01); H03K 17/06 (2006.01); H03K 17/10 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/84 (2013.01); H01L 21/845 (2013.01); H01L 27/06 (2013.01); H01L 27/0629 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H01L 27/1211 (2013.01); H01L 29/4236 (2013.01); H01L 29/78 (2013.01); H03K 17/063 (2013.01); H03K 17/102 (2013.01);
Abstract

A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.


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