The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

May. 31, 2013
Applicant:

Hrl Laboratories, Llc, Malibu, CA (US);

Inventors:

Hasan Sharifi, Agoura Hills, CA (US);

Keisuke Shinohara, Thousand Oaks, CA (US);

Mary C. Montes, West Hills, CA (US);

Charles McGuire, Newbury Park, CA (US);

Wonill Ha, Thousand Oaks, CA (US);

Jason May, Marina Del Rey, CA (US);

Hooman Kazemi, Thousand Oaks, CA (US);

Jongchan Kang, Moorpark, CA (US);

Robert G. Nagele, Thousand Oaks, CA (US);

Assignee:

HRL Laboratories, LLC, Malibu, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/12 (2006.01); H01L 21/58 (2006.01);
U.S. Cl.
CPC ...
H01L 23/12 (2013.01); H01L 21/58 (2013.01);
Abstract

An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dielectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.


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