The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Oct. 07, 2015
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, Kanagawa, JP;

Inventor:

Takahito Harada, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-Shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/053 (2006.01); H01L 25/07 (2006.01); H01L 23/051 (2006.01); H01L 23/498 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/433 (2006.01); H01L 23/492 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/053 (2013.01); H01L 23/051 (2013.01); H01L 23/367 (2013.01); H01L 23/3675 (2013.01); H01L 23/3735 (2013.01); H01L 23/4334 (2013.01); H01L 23/492 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 24/33 (2013.01); H01L 25/0657 (2013.01); H01L 25/07 (2013.01); H01L 21/486 (2013.01); H01L 23/3107 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/19107 (2013.01);
Abstract

A semiconductor module includes a printed circuit board having an insulating plate, first and fourth wiring layers disposed on a principal surface of the insulating plate, second and third wiring layers disposed on another surface opposite to the principal surface, a first via disposed in the insulating plate and electrically and mechanically connected to the first and third wiring layers, and a second via disposed in the insulating plate and electrically and mechanically connected to the second and fourth wiring layers; a first insulating substrate disposed with a first circuit plate; a second insulating substrate disposed with a second circuit plate; a first semiconductor chip; a second semiconductor chip; a first heat release member fixed between the third wiring layer and the third circuit plate; and a second heat release member fixed between the fourth wiring layer and the first circuit plate.


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