The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2016
Filed:
Sep. 25, 2013
Applicant:
Cree, Inc., Durham, NC (US);
Inventors:
Zoltan Ring, Chapel Hill, NC (US);
Dan Namishia, Wake Forest, NC (US);
Assignee:
Cree, Inc., Durham, NC (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/04 (2006.01); H01L 21/285 (2006.01); H01L 21/443 (2006.01); H01L 21/311 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 21/049 (2013.01); H01L 21/0495 (2013.01); H01L 21/28587 (2013.01); H01L 21/31116 (2013.01); H01L 21/443 (2013.01); H01L 29/66621 (2013.01); H01L 29/66863 (2013.01); H01L 21/28114 (2013.01); H01L 21/28123 (2013.01); H01L 29/2003 (2013.01); H01L 29/42376 (2013.01); H01L 29/6656 (2013.01); H01L 29/66553 (2013.01);
Abstract
Provided are devices including ultra-short gates and methods of forming same. Methods include forming a first gate pattern on a semiconductor that includes a first recess having a first width. A dielectric spacer is formed on a sidewall of the first recess to define a second recess in the first recess that has a second width that is smaller than the first width. A gate having the second width is formed in the second recess.