The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2016
Filed:
Jul. 27, 2015
Applicant:
SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;
Inventor:
Hee Jin Byun, Icheon-si, KR;
Assignee:
SK HYNIX INC., Icheon-Si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 8/18 (2006.01); G11C 8/04 (2006.01); G11C 8/06 (2006.01); G11C 8/12 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/109 (2013.01); G11C 7/1039 (2013.01); G11C 7/1084 (2013.01); G11C 7/1087 (2013.01); G11C 7/1093 (2013.01); G11C 7/22 (2013.01); G11C 8/04 (2013.01); G11C 8/06 (2013.01); G11C 8/12 (2013.01); G11C 8/18 (2013.01);
Abstract
A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.
Byun, Hee. (2016). Semiconductor integrated circuit including semiconductor memory apparatus including a plurality of banks (U.S. Patent No. 9530474). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9530474
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile