The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9530469 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 27, 2016

Filed:

Mar. 15, 2013
Applicant:

Sony Corporation, Tokyo, JP;

Inventors:

Makoto Kitagawa, Boise, ID (US);

Tomohito Tsushima, Tokyo, JP;

Wataru Otsuka, Boise, ID (US);

Takafumi Kunihiro, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 7/18 (2013.01);
Abstract

An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line.


Find Patent Forward Citations

Kitagawa, Makoto. (2016). Integrated circuit system with non-volatile memory stress suppression and method of manufacture thereof (U.S. Patent No. 9530469). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9530469

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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