The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Jul. 06, 2012
Applicants:

Sumanth Jannyavula Venkata, Shakopee, MN (US);

James David Sawin, Sterling, MA (US);

Yunaldi Yulizar, Shakopee, MN (US);

Ryan James Goss, Prior Lake, MN (US);

Inventors:

Sumanth Jannyavula Venkata, Shakopee, MN (US);

James David Sawin, Sterling, MA (US);

Yunaldi Yulizar, Shakopee, MN (US);

Ryan James Goss, Prior Lake, MN (US);

Assignee:

SEAGATE TECHNOLOGY LLC, Cupertino, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/02 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0866 (2013.01); G06F 3/0614 (2013.01); G06F 12/0246 (2013.01);
Abstract

Approaches for implementing a controller for a hybrid memory that includes a main memory and a cache for the main memory are discussed. The controller comprises a hierarchy of abstraction layers, wherein each abstraction layer is configured to provide at least one component of a cache management structure. Each pair of abstraction layers utilizes processors communicating through an application programming interface (API). The controller is configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers.


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