Apparatuses and methods to enhance timing delay fault coverage

Abstract

Described herein are apparatuses and methods for enhancing timing delay fault coverage during testing of functional circuitry. The present design includes a novel at-speed (e.g., at clock speed of functional circuitry during functional mode) mechanism to improve transition delay fault testing. In one embodiment, an apparatus includes functional circuitry for performing functional operations and test logic coupled to the functional circuitry. The test logic enhances timing delay fault coverage for the functional circuitry. The test logic includes scan flip-flops arranged in at least one scan chain and at least one input signal that is generated based on at least one scan override signal for overriding at least one scan enable signal.