The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2016

Filed:

Apr. 08, 2014
Applicant:

Finisar Corporation, Sunnyvale, CA (US);

Inventors:

Henry Meyer Daghighian, Menlo Park, CA (US);

Steven C. Bird, San Jose, CA (US);

Gerald Douglas Babel, Danville, CA (US);

Assignee:

FINISAR CORPORATION, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/46 (2006.01); H05K 3/24 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4688 (2013.01); H05K 3/244 (2013.01); H05K 1/024 (2013.01); H05K 1/0366 (2013.01); H05K 2201/0141 (2013.01); H05K 2201/0154 (2013.01); H05K 2201/0191 (2013.01);
Abstract

A hybrid printed circuit board may include a top layer, a bottom layer, and a plurality of internal layers stacked up between the top layer and the bottom layer. The plurality of internal layers may include a first internal layer below the top layer and a second internal layer above the bottom layer. The hybrid printed circuit board may include first unreinforced laminate placed between the top layer and the first internal layer. The hybrid circuit board may additionally include second unreinforced laminate placed between the second internal layer and the bottom layer. The hybrid printed circuit board may include third laminate placed between adjacent internal layers of the plurality of internal layers.


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