The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 20, 2016
Filed:
Feb. 17, 2014
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Woon Taek Oh, Seongnam-si, KR;
Jin Ho Kim, Suwon-si, KR;
Tae Jin Kim, Seoul, KR;
Jae Youl Lee, Hwaseong-si, KR;
Young Hwan Chang, Seoul, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H04L 7/033 (2006.01); G09G 5/02 (2006.01); G11C 7/10 (2006.01); G09G 3/20 (2006.01); H03L 7/095 (2006.01); G11C 7/22 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0331 (2013.01); G09G 3/20 (2013.01); G09G 5/02 (2013.01); G11C 7/1096 (2013.01); H03L 7/095 (2013.01); H04L 7/033 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0267 (2013.01); G11C 7/222 (2013.01);
Abstract
A phase locked loop includes a voltage controlled oscillator including a plurality of delay cells configured to respectively generate a plurality of clock signals having different phases and a harmonic lock detector configured to detect harmonic lock in the voltage controlled oscillator and to generate a reset signal in response. Remaining ones of the delay cells other than a first delay cell among the plurality of delay cells are reset in response to the reset signal.