The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2016

Filed:

Mar. 17, 2016
Applicant:

Kabushiki Kaisha Toshiba, Toyko, JP;

Inventor:

Masato Oda, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01); H03K 19/177 (2006.01); H03K 19/173 (2006.01); G11C 13/00 (2006.01); G11C 11/41 (2006.01); G11C 29/50 (2006.01); G11C 17/18 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1776 (2013.01); G11C 13/0069 (2013.01); H03K 19/1737 (2013.01); H03K 19/17728 (2013.01); G11C 11/41 (2013.01); G11C 17/18 (2013.01); G11C 2029/5006 (2013.01);
Abstract

According to an embodiment, a reconfigurable semiconductor integrated circuit includes memories connected in parallel, a logic circuit whose logic is defined according to data output of one of the memories, a signal output unit, and a switching unit. The signal output unit includes output terminals corresponding to the respective memories. Each terminal outputs a selection signal for enabling the data output or a non-selection signal for disabling the data output to the logic circuit. The signal output unit is configured to output the selection signal in a cyclic manner over the terminals so that one terminal outputs the selection signal and the others output the non-selection signal. The switching unit is configured to set a route between a first output terminal and a second output terminal of the terminals to an open state or a closed state. The route bypasses at least a single output terminal.


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