The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2016

Filed:

Mar. 05, 2014
Applicant:

Mediatek Singapore Pte. Ltd., Singapore, SG;

Inventors:

Uday Dasgupta, Singapore, SG;

Decheng Song, Singapore, SG;

Ming Kong, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 3/45 (2006.01); H03F 3/30 (2006.01); H03F 3/21 (2006.01);
U.S. Cl.
CPC ...
H03F 3/45179 (2013.01); H03F 3/211 (2013.01); H03F 3/3023 (2013.01); H03F 3/45192 (2013.01); H03F 3/45632 (2013.01); H03F 3/45654 (2013.01); H03F 2203/21127 (2013.01); H03F 2203/45028 (2013.01); H03F 2203/45051 (2013.01); H03F 2203/45062 (2013.01); H03F 2203/45064 (2013.01); H03F 2203/45074 (2013.01); H03F 2203/45082 (2013.01); H03F 2203/45112 (2013.01); H03F 2203/45122 (2013.01); H03F 2203/45126 (2013.01); H03F 2203/45134 (2013.01); H03F 2203/45154 (2013.01); H03F 2203/45176 (2013.01); H03F 2203/45178 (2013.01); H03F 2203/45194 (2013.01); H03F 2203/45244 (2013.01); H03F 2203/45274 (2013.01); H03F 2203/45278 (2013.01); H03F 2203/45301 (2013.01); H03F 2203/45302 (2013.01); H03F 2203/45418 (2013.01); H03F 2203/45424 (2013.01); H03F 2203/45434 (2013.01); H03F 2203/45642 (2013.01); H03F 2203/45672 (2013.01); H03F 2203/45691 (2013.01);
Abstract

A differential amplifier and a method thereof are described. The method, adopted by a differential amplifier, includes: generating first stage differential output signals based on input differential signals; providing, by a current source, a bias current with a desired quiescent current; biasing first and second control transistors with the bias current to generate first and second currents, respectively, wherein the first and second control transistors form a differential pair which receives first stage differential input signals; mirroring the first and second currents to first and second push transistors which are connected to first and second pull transistors in series, respectively; and biasing the first and second pull transistors with the mirrored first and second currents, respectively; wherein each pair of serial connected push and pull transistors are complimentary and the two pairs of push and pull transistors output second stage differential output signals.


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