The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2016

Filed:

Apr. 30, 2015
Applicant:

Samsung Electronics Co., Ltd., Gyeonggi-do, KR;

Inventors:

Seokjun Won, Seoul, KR;

Youngmook Oh, Gyeonggi-do, KR;

Moonkyun Song, Gyeonggi-do, KR;

MinWoo Song, Gyeonggi-do, KR;

Namgyu Cho, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6656 (2013.01); H01L 21/28008 (2013.01); H01L 21/31111 (2013.01); H01L 21/762 (2013.01); H01L 21/823456 (2013.01); H01L 21/823468 (2013.01); H01L 21/823481 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 29/6653 (2013.01); H01L 29/66553 (2013.01);
Abstract

A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.


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