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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9524925 B1

PDFFull Text
Date of Patent:
Dec. 20, 2016

Filed:

Apr. 12, 2016

Method of manufacturing a semiconductor device

Applicant:

Sony Corporation, Tokyo, JP;

Inventors:

Satoru Wakiyama, Kanagawa, JP;

Masaki Okamoto, Kumamoto, JP;

Yutaka Ooka, Kanagawa, JP;

Reijiroh Shohji, Tokyo, JP;

Yoshifumi Zaizen, Kanagawa, JP;

Kazunori Nagahata, Kanagawa, JP;

Masaki Haneda, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:

Sheridan Ross P.C.

Primary Examiner:

Thao P Le

Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 27/1469 (2013.01); H01L 27/14632 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14687 (2013.01); H01L 2224/32145 (2013.01); H01L 2225/06541 (2013.01);
Abstract

There is provided a method for manufacturing a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.

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