The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2016

Filed:

Sep. 10, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Nathan Fontenot, Georgetown, TX (US);

Ryan Patrick Grimm, Austin, TX (US);

Robert Cory Jennings, Jr., Austin, TX (US);

Joel Howard Schopp, Austin, TX (US);

Michael Thomas Strosaker, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0891 (2016.01); G06F 12/14 (2006.01); G06F 5/06 (2006.01); G06F 9/46 (2006.01); G06F 13/16 (2006.01); G06F 5/14 (2006.01); G06F 12/08 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0891 (2013.01); G06F 5/065 (2013.01); G06F 9/467 (2013.01); G06F 12/1466 (2013.01); G06F 12/1475 (2013.01); G06F 13/1663 (2013.01); G06F 5/14 (2013.01); G06F 2205/067 (2013.01); G06F 2212/1052 (2013.01);
Abstract

A system and computer program product for resetting of memory locks in a transactional memory system. The system includes a processor setting at least one new memory lock during execution of a transaction that acquires access to a region of memory. The new memory lock indicates that the transaction and its associated thread have exclusive temporary access to the memory region. The system further includes the processor determining if a first in first out (FIFO) memory lock register is full of memory locks and, in response to the FIFO memory lock register being full, a memory lock is removed from a tail position of the FIFO memory lock register. The removed memory lock is reset to return to a transactional memory state and the new memory lock is added to a head position in the FIFO memory lock register.


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