The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2016

Filed:

Feb. 04, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Raymond Keith Rosik, San Diego, CA (US);

Steven M. Bidermann, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/24 (2006.01); G01R 19/165 (2006.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
G06F 1/24 (2013.01); G01R 19/16552 (2013.01); G06F 1/26 (2013.01); G06F 11/2268 (2013.01);
Abstract

In one embodiment, a power management integrated circuit comprises a finite state machine having a first terminal to receive a digital command signal, a second terminal to receive a clock signal, and a third terminal to receive a first reset signal to reset the finite state machine into a predetermined operational state. A plurality of diagnostic registers is configured to store a signal state of the digital command signal or a clock state of the clock signal, or both in response to the first reset signal. The diagnostic registers are configured to maintain the signal state or the clock state, or both after powering down of the power management integrated circuit in response to the first reset signal. The diagnostic registers are configured to allow retrieval of the stored signal state or the stored clock state, or both upon power on of the power management integrated circuit.


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