The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2016

Filed:

Mar. 11, 2016
Applicant:

Avnera Corporation, Beaverton, OR (US);

Inventor:

Christopher D. Nilson, San Jose, CA (US);

Assignee:

AVNERA CORPORATION, Beaverton, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/66 (2006.01); G05F 3/26 (2006.01); H03M 1/00 (2006.01); H03M 1/74 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
H03M 1/66 (2013.01); G05F 3/262 (2013.01); H03M 1/00 (2013.01); H03M 1/12 (2013.01); H03M 1/747 (2013.01);
Abstract

A current-mode, digital-to-analog converter (DAC) configured to convert a digital word input having j bits to an analog signal. The DAC has 2current sources, an output node, a current divider, a first switch, and a second switch. Each of the 2current sources is configured to produce a current having a value I. The current divider has a programmable divide ratio, d, where 1/d is between 0 and 1. The first switch is configured to selectively couple 2−1 of the 2current sources to the output node. One of the 2current sources is not coupled to the output node. The second switch is configured to selectively couple each of the 2j current sources to the current divider. This architecture ensures that the fundamental transform of input code to output current always has a slope that does not change from positive to negative or from negative to positive.


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