The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2016
Filed:
Mar. 31, 2016
Cypress Semiconductor Corporation, San Jose, CA (US);
Ramesh Chettuvetty, Bengaluru, IN;
Sonal Chandrasekharan, Bengaluru, IN;
Andrew J. Wright, Fremont, CA (US);
Hiromu Takehara, Tokyo, JP;
Ashok Kumar, Bengaluru, IN;
Tushar Kachhdiya, Raleigh, NC (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
An integrated circuit (IC) device can include at least one phase or delay lock loop (P/DLL) circuit comprising a plurality of circuit sections, at least one of the circuit sections responsive to digital calibration values to alter at least one periodic output signal; a nonvolatile memory (NVM) circuit formed in the same IC package as the at least one P/DLL circuit and configured to store the calibration values; and a processing circuit formed in the same IC package as the at least one P/DLL circuit and the NVM circuit, the processing circuit configured to generate the calibration values in response to target values and output values from the at least one P/DLL circuit, and to store the calibration values in the NVM circuit.