The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2016

Filed:

Apr. 25, 2013
Applicants:

Mohammad Fakharzadeh, Toronto, CA;

Mihai Tazlauanu, Markham, CA;

Inventors:

Mohammad Fakharzadeh, Toronto, CA;

Mihai Tazlauanu, Markham, CA;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01P 5/08 (2006.01); H01P 11/00 (2006.01); H01P 5/107 (2006.01); H01Q 21/00 (2006.01); H01Q 13/02 (2006.01);
U.S. Cl.
CPC ...
H01P 5/08 (2013.01); H01P 5/107 (2013.01); H01P 11/00 (2013.01); H01P 11/001 (2013.01); H01Q 13/02 (2013.01); H01Q 21/0075 (2013.01); Y10T 29/49016 (2015.01);
Abstract

An apparatus includes an IC package comprising a substrate having a first metal layer, a second metal layer, and a dielectric layer disposed between the first and second metal layers. The IC package further comprises an IC die disposed at a surface of the substrate and comprising RF circuitry. The first metal layer comprises a microstrip feedline extending from a pin of the IC die. The microstrip feedline includes a conductive trace having a probe element at a tip distal from the pin. The first metal layer further comprises a waveguide opening comprising a region surrounding the probe element, the region being substantially devoid of conductive material. The substrate further comprises a plurality of metal vias disposed at the perimeter of the region, the metal vias extending from the first metal layer to the second metal layer.


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