The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2016

Filed:

Jun. 19, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Xiongfei Meng, Carlsbad, CA (US);

Joon Hyung Chung, San Marcos, CA (US);

Yuancheng Christopher Pan, Saratoga, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 27/06 (2006.01); H01L 23/66 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 23/66 (2013.01); H01L 27/0617 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An apparatus including a conductive stack structure includes an Mlayer interconnect on an Mlayer and extending in a first direction on a first track, an Mlayer interconnect on an Mlayer in which the Mlayer is a lower layer than the Mlayer, a first via stack coupled between the Mlayer interconnect and the Mlayer interconnect, a second via stack coupled between the Mlayer interconnect and the Mlayer interconnect, a second Mlayer interconnect extending in the first direction on a track immediately adjacent to the first track, and a third Mlayer interconnect extending in the first direction on a track immediately adjacent to the first track. The Mlayer interconnect is between the second Mlayer interconnect and the third Mlayer interconnect. The second Mlayer interconnect and the third Mlayer interconnect are uncoupled to each other.


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