The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2016

Filed:

Jul. 02, 2014
Applicant:

Toppan Printing Co., Ltd., Tokyo, JP;

Inventors:

Kenta Hayashi, Tokyo, JP;

Katsumi Yamamoto, Tokyo, JP;

Makoto Nakamura, Tokyo, JP;

Naoyuki Akiyama, Tokyo, JP;

Kyosuke Taguchi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 21/3065 (2006.01); H01L 27/146 (2006.01); H01L 21/311 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76814 (2013.01); H01L 21/3065 (2013.01); H01L 21/30655 (2013.01); H01L 21/31116 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 27/14618 (2013.01); H01L 27/14636 (2013.01); H01L 27/14683 (2013.01); H01L 23/525 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13024 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate including a first surface in which an integrated circuit and an I/O pad electrically connected to the integrated circuit are formed, and a second surface which is an opposite side to the first surface, where a two-stage through-hole is formed in the semiconductor substrate, the semiconductor substrate including a first shape portion having a tapered shape which has a wall surface and of which a diameter of an opening becomes smaller toward a bottom of the hole from the second surface side to a predetermined position of the semiconductor substrate in a thickness direction, and including a second shape portion having a cylindrical shape which extends from the first shape portion to the I/O pad on the first surface side, and that includes an inorganic insulating film which is formed on the wall surface of the two-stage through-hole and the second surface.


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