The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2016

Filed:

Aug. 21, 2015
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Tomoaki Inokuchi, Yokohama, JP;

Mizue Ishikawa, Yokohama, JP;

Hideyuki Sugiyama, Kawasaki, JP;

Yoshiaki Saito, Kawasaki, JP;

Tetsufumi Tanamoto, Kawasaki, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/15 (2006.01); G11C 11/16 (2006.01); H01L 43/08 (2006.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/161 (2013.01); G11C 11/15 (2013.01); G11C 11/1659 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/1693 (2013.01); H01L 27/224 (2013.01); H01L 27/228 (2013.01); H01L 43/08 (2013.01); G11C 2213/72 (2013.01); G11C 2213/74 (2013.01); G11C 2213/79 (2013.01);
Abstract

A resistive change memory according to an embodiment includes: a memory cell including a resistive change element comprising a first and second terminals, and a semiconductor element, the semiconductor element including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, and a third semiconductor layer of a second conductivity type that is different from the first conductivity type, the third semiconductor layer being disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer being connected to the second terminal of the resistive change element; and a read unit configured to perform a read operation by applying a first read voltage between the first terminal and the second semiconductor layer, and then applying a second read voltage that is lower than the first read voltage between the first terminal and the second semiconductor layer.


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