The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2016
Filed:
Jan. 02, 2015
Applicant:
Vmware, Inc., Palo Alto, CA (US);
Inventors:
Benjamin C. Serebrin, Sunnyvale, CA (US);
Bhavesh Mehta, Mountain View, CA (US);
Assignee:
VMware, Inc., Palo Alto, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/14 (2006.01); G06F 12/10 (2016.01); G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1451 (2013.01); G06F 11/1464 (2013.01); G06F 12/1018 (2013.01); G06F 12/1027 (2013.01); G06F 2009/45583 (2013.01); G06F 2201/815 (2013.01); G06F 2201/84 (2013.01); G06F 2212/651 (2013.01); G06F 2212/657 (2013.01);
Abstract
One or more unused bits of a virtual address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2)-th of a memory page.