The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2016

Filed:

Jan. 20, 2014
Applicant:

Lenovo Enterprise Solutions (Singapore) Pte. Ltd., Singapore, SG;

Inventors:

Jonathan L. Kaus, Rochester, MN (US);

Adam C. Lange-Pearson, Rochester, MN (US);

Gary R. Ricard, Chatfield, MN (US);

Jaimeson Saley, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); G06F 13/24 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0745 (2013.01); G06F 9/38 (2013.01); G06F 11/0706 (2013.01); G06F 11/0721 (2013.01); G06F 11/0784 (2013.01); G06F 11/0793 (2013.01); G06F 13/24 (2013.01); G06F 11/0772 (2013.01); G06F 2201/81 (2013.01); G06F 2211/002 (2013.01);
Abstract

A method, processor, and computer system for handling interrupts within a hierarchical register structure. The method includes receiving at a root-level register an indication of an interrupt occurring at a lower level register in the register structure, using a system interrupt handler to invoke an error handler assigned to a set of registers of the structure that includes the lower level register, and using the invoked error handler to handle the interrupt and return to the system interrupt handler.


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