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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9516764 B1

PDFFull Text
Date of Patent:
Dec. 06, 2016

Filed:

Mar. 25, 2014

Method for manufacturing multilayer wiring substrate

Applicant:

Hitachi Chemical Company, Ltd., Tokyo, JP;

Inventor:

Nobuyuki Yoshida, Tokyo, JP;

Assignee:

HITACHI CHEMICAL COMPANY, LTD, Tokyo, JP;

Attorney:

Fitch, Even, Tabin & Flannery, LLP

Primary Examiner:

Lan Vinh

Int. Cl.
CPC ...
H01B 13/00 (2006.01); H05K 3/42 (2006.01); C25D 7/00 (2006.01); C25D 5/02 (2006.01); C25D 5/10 (2006.01); C25D 5/48 (2006.01); C23C 18/16 (2006.01); H05K 3/06 (2006.01); C25D 3/38 (2006.01); C25D 5/34 (2006.01); C25D 7/12 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 1/09 (2006.01); H05K 1/11 (2006.01); H05K 3/46 (2006.01); C23C 18/40 (2006.01); H05K 3/38 (2006.01);
U.S. Cl.
CPC ...
H05K 3/421 (2013.01); C23C 18/1653 (2013.01); C25D 3/38 (2013.01); C25D 5/02 (2013.01); C25D 5/10 (2013.01); C25D 5/34 (2013.01); C25D 5/48 (2013.01); C25D 7/00 (2013.01); C25D 7/123 (2013.01); H05K 1/0298 (2013.01); H05K 1/0346 (2013.01); H05K 1/09 (2013.01); H05K 1/115 (2013.01); H05K 3/06 (2013.01); H05K 3/427 (2013.01); C23C 18/405 (2013.01); H05K 3/382 (2013.01); H05K 3/4652 (2013.01); H05K 3/4661 (2013.01); H05K 2201/0154 (2013.01); H05K 2201/0355 (2013.01); H05K 2201/09545 (2013.01); H05K 2201/09563 (2013.01); H05K 2203/0353 (2013.01); H05K 2203/1423 (2013.01);
Abstract

To provide a method for manufacturing a multilayer wiring substrate, in which an insulating layer and a metal foil provided thereon are integrally laminated on an inner layer material having a wiring formed thereon, in which a hole for via hole is formed in the metal foil and the insulating layer, and in which the hole for via hole is filled with an electrolytic filled plating layer after a base electroless plating layer is formed, the method being featured in that, after the base electroless plating layer is formed, first, an electrolysis filled plating layer is formed to the extent that the hole for via hole is not completely filled, and then, after the surface of the electrolytic filled plating layer is etched, the hole for via hole is completely filled by an electrolytic filled plating layer.

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