The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2016

Filed:

Oct. 03, 2014
Applicant:

Crestron Electronics, Inc., Rockleigh, NJ (US);

Inventors:

Christopher Merck, Union City, NJ (US);

Andrew Salmon, PlainField, NJ (US);

Gennady Pratusevich, West Nyack, NY (US);

Assignee:

Crestron Electronics Inc., Rockleigh, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/721 (2013.01); H04L 12/705 (2013.01); H04L 12/935 (2013.01); H04L 12/931 (2013.01); H04L 12/24 (2006.01);
U.S. Cl.
CPC ...
H04L 45/44 (2013.01); H04L 41/12 (2013.01); H04L 45/18 (2013.01); H04L 45/66 (2013.01); H04L 49/351 (2013.01);
Abstract

A master Ethernet bridge for use in an Ethernet network that includes a master central processing unit and associated master Ethernet switch, and one or more slave central processing units, each having an associated slave Ethernet switch, each of the associated slave Ethernet switches connected to a plurality of input/output ports, and wherein each of the plurality of ports is assigned a respective port number, each of the ports being connected to one of the one or more of the cascaded Ethernet devices, and wherein each of the master CPU and slave CPUs includes memory that contains a program that embodies a plurality of Ethernet functions adapted to substantially prevent re-routing of Ethernet commands by providing a mapping function that correlates the plurality of ports to respective ones of the one or more slave CPU and slave Ethernet switch.


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