The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2016

Filed:

Jun. 20, 2013
Applicant:

Nordic Semiconductor Asa, Trondheim, NO;

Inventors:

Markus Bakka Hjerto, Oslo, NO;

Frank Berntsen, Heimdal, NO;

Assignee:

NORDIC SEMICONDUCTOR ASA, Trondheim, NO;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 27/26 (2006.01); G06F 5/06 (2006.01); H04B 1/7156 (2011.01); H04B 1/7073 (2011.01);
U.S. Cl.
CPC ...
H04L 7/0008 (2013.01); G06F 5/06 (2013.01); H04L 27/2655 (2013.01); H04B 1/7073 (2013.01); H04B 1/7156 (2013.01);
Abstract

An arrangement for transferring a data signal from a first clock domain (bus_slow) to a second clock domain (bus_fast) in a digital system. The first clock domain (bus_slow) has a first clock (ck slow) with a frequency less than a frequency of a second clock (ck fast) in the second clock domain (bus_fast). The arrangement is configured to transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast), detect whether a predetermined transition occurs in the first clock (ck slow) within a predetermined period of time, using detecting means () clocked by the second clock (ck fast), and transfer the data signal from the first clock domain (bus_slow) to the second clock domain (bus_fast) again if the detecting means () detects the predetermined transition in the first clock (ck slow) within the predetermined period of time.


Find Patent Forward Citations

Loading…