The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2016
Filed:
Aug. 25, 2015
Gukhyon Yon, Hwaseong-si, KR;
Jaeyoung Ahn, Seongnam-si, KR;
Bio Kim, Seoul, KR;
Young-jin Noh, Suwon-si, KR;
Kwangmin Park, Seoul, KR;
Dongchul Yoo, Seongnam-si, KR;
Gukhyon Yon, Hwaseong-si, KR;
Jaeyoung Ahn, Seongnam-si, KR;
Bio Kim, Seoul, KR;
Young-Jin Noh, Suwon-si, KR;
Kwangmin Park, Seoul, KR;
Dongchul Yoo, Seongnam-si, KR;
SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;
Abstract
Provided are a three dimensional semiconductor memory device and a method of fabricating the same. In the three dimensional semiconductor memory device, a stack of gate electrodes and insulating layers may be formed on a substrate, a channel structure may extend through the stack and connect to the substrate. A blocking insulating layer, a charge storing layer and a tunnel insulating layer may be formed between each gate electrode and the channel structure. The tunnel insulating layer may include a high-k dielectric layer with a low charge trap site density. The tunnel insulating layer may also include a first and a second tunnel insulating layers, and the high-k dielectric layer is provided between the first and second tunnel insulating layers.