The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9515023 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 06, 2016

Filed:

Mar. 10, 2015
Applicant:

Sandisk 3d Llc, Milpitas, CA (US);

Inventors:

Toshihide Tobitsuka, Yokkaichi, JP;

Seje Takaki, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 27/115 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/76895 (2013.01); H01L 27/1157 (2013.01); H01L 27/11548 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11578 (2013.01); H01L 27/11582 (2013.01); H01L 27/2481 (2013.01); H01L 27/249 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A multi-level device includes at least one device region and at least one contact region. The contact region has a stack of alternating plurality of electrically conductive layers and plurality of electrically insulating layers located over a substrate. The plurality of electrically conductive layers form a stepped pattern in the contact region, where each respective electrically insulating layer includes a sidewall and a respective underlying electrically conductive layer in the stack extends laterally beyond the sidewall. Optionally, a plurality of electrically conductive via connections can be formed, which have top surfaces within a same horizontal plane, have bottom surfaces contacting a respective electrically conductive layer located at different levels, and are isolated from one another by at least one trench isolation structure.


Find Patent Forward Citations

Tobitsuka, Toshihide. (2016). Multilevel contact to a 3d memory array and method of making thereof (U.S. Patent No. 9515023). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9515023

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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