The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2016
Filed:
Jun. 01, 2016
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Se-Han Kwon, Gyeonggi-do, KR;
Ill-Hee Joe, Gyeonggi-do, KR;
Dae-Sik Park, Gyeonggi-do, KR;
Hwa-Chul Lee, Gyeonggi-do, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 21/764 (2006.01); H01L 27/105 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/764 (2013.01); H01L 27/1052 (2013.01); H01L 29/0649 (2013.01); H01L 21/7682 (2013.01);
Abstract
A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.