The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2016

Filed:

Jan. 08, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:
Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49503 (2013.01); H01L 21/4825 (2013.01); H01L 21/4842 (2013.01); H01L 21/561 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 24/32 (2013.01); H01L 24/49 (2013.01); H01L 24/73 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 24/92 (2013.01); H01L 24/97 (2013.01); H01L 23/49541 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48257 (2013.01); H01L 2224/49433 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92247 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor device has a leadframe with a first () and a parallel second surface, and an assembly pad () bordered by two opposing sides, which include a plurality of through-holes () from the first to the second pad surface. Another pad side includes one or more elongated windows () between the pad surfaces. The second pad surface includes a plurality of grooves. The leadframe further has a plurality of leads () with opposite elongated sides castellated by indents (). Layers () of bondable metals are restricted to localized areas surrounding bond spots. A semiconductor chip () is attached to the pad and wire-bonded () to the bond spots. A package () encapsulates the chip, wires, pad, and lead portions, and secures the leadframe into the package by filling the through-holes, windows, grooves, and indents.


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