The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2016

Filed:

Jan. 20, 2015
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Ofer Shapira, Herzliya, IL;

Eran Sharon, Rishon Lezion, IL;

Idan Alrod, Herzliya, IL;

Assignee:

SanDisk Technologies LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/04 (2006.01); G11C 29/00 (2006.01); G11C 16/34 (2006.01); G11C 16/14 (2006.01); G11C 11/56 (2006.01); G06F 11/10 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G06F 11/079 (2013.01); G06F 11/0751 (2013.01); G11C 16/14 (2013.01); G11C 29/04 (2013.01); G06F 11/1068 (2013.01); G11C 11/5628 (2013.01); G11C 29/883 (2013.01);
Abstract

A memory is released for use without pre-verification of its memory blocks as being defect free. Some memory blocks are subjected to a verification process when the computer memory is in use in order to verify a minimum number of memory blocks required for high performance program operation as being defect free. The verification process continues as the computer memory is in use in order to maintain the minimum number of memory blocks required for high performance operation in the verified defect free state. A verification mode of either no verification, delayed verification, or immediate verification is applied to memory blocks used for regular performance program operation. Delayed verification is maintained until an ability to recover the stored data is going to be lost. Immediate verification can be performed using bit error rate analysis. Some verification processes are performed using aggressive programming trim and/or multiple word line sensing for faster programming.


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