Logic configuration method for reconfigurable semiconductor device

Abstract

Provided is a logic configuration method for a semiconductor device having a plurality of memory units provided with a plurality of memory cells; each memory unit is configured to store truth table data in the memory cells thereof, the truth table data being for outputting a logic value in response to an address input, and to operate as a logic circuit; the memory units have n (where n is 2 or a higher integer) times two pairs of an input line and an output line; the n times two output lines from one memory unit among the memory units are connected to the n input lines of two other memory units; and the logic configuration method generates, on the basis of the circuit description describing the circuit configuration, a netlist having circuit connection information, extracts a logic cone from the netlist, and generates truth table data for the plurality of memory units, which constitute the logic cone, in the memory unit stage number corresponding to the number obtained by dividing the number of input lines to the logic cone by n/2.