The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2016
Filed:
May. 02, 2012
Stephen Jones, San Francisco, CA (US);
Philip Alexander Cuadra, San Francisco, CA (US);
Daniel Elliot Wexler, Soda Springs, CA (US);
Ignacio Llamas, Sunnyvale, CA (US);
Lacky V. Shah, Los Altos Hills, CA (US);
Jerome F. Duluk, Jr., Palo Alto, CA (US);
Christopher Lamb, San Jose, CA (US);
Stephen Jones, San Francisco, CA (US);
Philip Alexander Cuadra, San Francisco, CA (US);
Daniel Elliot Wexler, Soda Springs, CA (US);
Ignacio Llamas, Sunnyvale, CA (US);
Lacky V. Shah, Los Altos Hills, CA (US);
Jerome F. Duluk, Jr., Palo Alto, CA (US);
Christopher Lamb, San Jose, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
One embodiment of the present invention sets forth a technique for performing nested kernel execution within a parallel processing subsystem. The technique involves enabling a parent thread to launch a nested child grid on the parallel processing subsystem, and enabling the parent thread to perform a thread synchronization barrier on the child grid for proper execution semantics between the parent thread and the child grid. This technique advantageously enables the parallel processing subsystem to perform a richer set of programming constructs, such as conditionally executed and nested operations and externally defined library functions without the additional complexity of CPU involvement.