The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2016

Filed:

May. 29, 2014
Applicant:

Mill Computing, Inc., Palo Alto, CA (US);

Inventors:

Roger Rawson Godard, East Palo Alto, CA (US);

Arthur David Kahlich, Sunnyvale, CA (US);

David Arthur Yost, Los Altos, CA (US);

Assignee:

MILL COMPUTING, INC., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/22 (2006.01); G06F 9/30 (2006.01); G06F 9/40 (2006.01); G06F 9/445 (2006.01); G06F 9/32 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/321 (2013.01); G06F 9/3802 (2013.01); G06F 9/3814 (2013.01); G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06F 9/3889 (2013.01); G06F 9/324 (2013.01);
Abstract

A computer processor is operably coupled to a memory system. The memory system is configured to store instruction blocks, wherein each instruction block is associated with an entry address and multiple distinct instruction streams within the instruction block. The multiple distinct instruction streams include at least a first instruction stream and a second instruction stream. The first instruction stream has an instruction order that logically extends in a direction of increasing memory space relative to the entry address of the instruction block. The second instruction stream has an instruction order that logically extends in a direction of decreasing memory space relative to the entry address of the instruction block. The computer processor includes a number of multi-stage instruction processing components corresponding to the multiple distinct instruction streams within each instruction block. The number of multi-stage instruction processing components are configured to access and process in parallel instructions belonging to multiple distinct instruction streams of a particular instruction block stored in the memory system.


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