The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2016

Filed:

Nov. 07, 2011
Applicants:

Glenn A. Forrest, Bow, NH (US);

Aaron Cook, Deerfield, NH (US);

Dana Briere, Bedford, NH (US);

Devon Fernandez, Londonderry, NH (US);

Naota Nakayama, Nashua, NH (US);

Inventors:

Glenn A. Forrest, Bow, NH (US);

Aaron Cook, Deerfield, NH (US);

Dana Briere, Bedford, NH (US);

Devon Fernandez, Londonderry, NH (US);

Naota Nakayama, Nashua, NH (US);

Assignee:

Allegro Microsystems, LLC, Worcester, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318552 (2013.01); G01R 31/318594 (2013.01);
Abstract

An integrated circuit sensor includes circuitry and methods for generating a high speed delay fault test clock signal. A trimmable oscillator generates a master clock signal for use by an output protocol processor to provide the sensor output signal. A fault test clock signal generator is responsive to the master clock signal and to a test trigger signal for generating the test clock signal having a launch pulse and a capture pulse, each having edges substantially coincident with like edges of pulses of the master clock signal and a spacing between launch and capture pulses established by the trimmable master clock signal.


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