The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Aug. 19, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Vidhya Ramachandran, Cupertino, CA (US);

Urmi Ray, San Diego, CA (US);

Ravindra Vaman Shenoy, Dublin, CA (US);

Kwan-Yu Lai, Campbell, CA (US);

Jon Bradley Lasiter, Stockton, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 23/538 (2006.01); H01L 21/84 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01); H01L 23/14 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H05K 1/185 (2013.01); H01L 21/28008 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/84 (2013.01); H01L 23/147 (2013.01); H01L 23/49827 (2013.01); H01L 23/5384 (2013.01); H01L 25/065 (2013.01); H01L 27/0629 (2013.01); H01L 27/0688 (2013.01); H01L 27/12 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/15311 (2013.01);
Abstract

An integrated interposer between a first component and a second component includes a substrate. The substrate may have thermal and/or mechanical properties with values lying between the thermal and/or mechanical properties of the first component and the second component. Active devices are disposed on a first surface of the substrate. A contact layer is coupled to the active devices and configured to couple at least the first component and a third component to the integrated interposer. At least one through via(s) is coupled to the contact layer and extends through the substrate to a second surface of the substrate. An interconnect layer is disposed on the second surface of the substrate and coupled to the at least one through via(s). The interconnect layer is configured to couple the second component to the integrated interposer.


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