The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Mar. 04, 2014
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Oliver Haeberlen, Villach, AT;

Walter Rieger, Arnoldstein, AT;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01); H03K 17/56 (2006.01); H03K 17/567 (2006.01); H01L 27/085 (2006.01); H03K 3/012 (2006.01); H03K 17/06 (2006.01); H03K 17/12 (2006.01); H03K 17/14 (2006.01); H01L 29/778 (2006.01); H01L 27/06 (2006.01); H03K 17/687 (2006.01); H01L 29/40 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); H01L 27/0605 (2013.01); H01L 27/085 (2013.01); H01L 29/7786 (2013.01); H03K 17/063 (2013.01); H03K 17/122 (2013.01); H03K 17/145 (2013.01); H03K 17/16 (2013.01); H03K 17/56 (2013.01); H03K 17/567 (2013.01); H01L 29/2003 (2013.01); H01L 29/402 (2013.01); H03K 2017/6875 (2013.01); H03K 2217/0036 (2013.01);
Abstract

An electronic circuit includes a transistor arrangement with a plurality of transistor devices, each including a control node and a load path between a first load node and a second load node, and having the load paths connected in parallel. The electronic circuit further includes a drive circuit coupled to the control node of each of the plurality of transistor devices, and configured to receive an input signal. Each of the plurality of transistor devices includes a two-dimensional electron gas (2DEG) in the load path, and a field plate adjacent the 2DEG. The drive circuit is configured to receive a load signal that represents at least one load parameter of the transistor arrangement and is configured to one of activate and deactivate at least one of the plurality of transistor devices based on the load signal.


Find Patent Forward Citations

Loading…