The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Oct. 11, 2011
Applicants:

Virendra V. Rana, Los Gatos, CA (US);

Pranav Anbalagan, San Jose, CA (US);

Mehrdad M. Moslehi, Los Altos, CA (US);

Inventors:

Virendra V. Rana, Los Gatos, CA (US);

Pranav Anbalagan, San Jose, CA (US);

Mehrdad M. Moslehi, Los Altos, CA (US);

Assignee:

Solexel, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/18 (2006.01); H01L 31/0224 (2006.01); H01L 31/068 (2012.01); H01L 31/046 (2014.01); H01L 31/056 (2014.01); H01L 31/0236 (2006.01); H01L 31/0352 (2006.01); H01L 31/0445 (2014.01); B23K 26/40 (2014.01);
U.S. Cl.
CPC ...
H01L 31/18 (2013.01); B23K 26/364 (2015.10); B23K 26/40 (2013.01); H01L 31/02363 (2013.01); H01L 31/022441 (2013.01); H01L 31/035281 (2013.01); H01L 31/046 (2014.12); H01L 31/0445 (2014.12); H01L 31/056 (2014.12); H01L 31/068 (2013.01); H01L 31/0682 (2013.01); H01L 31/1804 (2013.01); H01L 31/1896 (2013.01); B23K 2203/172 (2015.10); B23K 2203/50 (2015.10); Y02E 10/52 (2013.01); Y02E 10/547 (2013.01); Y02P 70/521 (2015.11);
Abstract

A method for making a crystalline silicon solar cell substrate is provided. A doped dielectric layer is deposited over the backside surface of a crystalline silicon substrate, the doped dielectric layer having a polarity opposite the polarity of the crystalline silicon substrate. Portions of the backside surface of the crystalline substrate are exposed through the doped dielectric layer. An overlayer is deposited over the doped dielectric layer and the exposed portions of the backside surface of the crystalline silicon substrate. Pulsed laser ablation of the overlayer is performed with a flat top laser beam on the silicon substrate to form continuous base openings nested within the exposed portions of the backside surface of the crystalline silicon substrate, the flat top laser beam having a beam intensity profile flatter as compared to a Gaussian beam intensity profile and having a rectangular beam cross section. Doped base regions are formed in the crystalline silicon substrate through the continuous base openings.


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